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What is the Race Condition in Verilog?

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What is the Race Condition in Verilog?

Post by degalabalaji1992 on Tue Oct 06, 2015 2:57 pm

When Two statements are trying to execute at Same Time Instant is defined as a Race Condition.

Illustration:- Swapping of Two values will easily explains the Race Condition assume a = 1 & b =0
always @(*) begin
a = b;
b = a;
end
If you observe the above statements those are written by using Blocking Assignments.so Both will be Executed in Active Event Region.when b is assigned to a i.e a=0,then in the Same time region the Updated value of a (i.e a =0 by Previous Statement) is assigned to b. So now b Value is again 0. so this type of Situation is called as Race Condition.

To avoid this problem we are going for Non Blocking Assignment Statements which will evaluate the R.H.S values in Active Event Region and Updated in NBA Region(Which will helps to avoid the Unwanted races caused by Blocking Assignments).



degalabalaji1992

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